1516 doc #97029 data delay devices, inc. 1 2/7/97 3 mt. prospect ave. clifton, nj 07013 5-tap dip/smd delay line t d /t r = 3 (series 1516) features packages 5 taps of equal delay increment delays to 200ns low profile epoxy encapsulated meets or exceeds mil-d-23859c functional description the 1516-series device is a fixed, single-input, five- output, passive delay line. the signal input (in) is reproduced at the outputs (t1-t5) in equal increments. the delay from in to t5 (t d ) and the characteristic impedance of the line (z) are determined by the dash number. the rise time (t r ) of the line is 30% of t d , and the 3db bandwidth is given by 1.05 / t d . the device is available in a 8-pin dip (1516) or a 8-pin smd (1516s), and a wide range of pinouts may be specified. part numbers are constructed according to the scheme shown at right. for example, 1516c-101-500b is a 290 mil dip, 100ns, 50 w delay line with pinout code b. similarly, 1516sb-151-501 is a 240 mil smd, 150ns, 500 w delay line with standard pinout. series specifications dielectric breakdown: 50 vdc distortion @ output: 10% max. operating temperature: -55 c to +125 c storage temperature: -55 c to +125 c temperature coefficient: 100 ppm/ c pinout codes code in t1 t2 t3 t4 t5 gnd std 2 3 4 5 6 7 1,8 a 1 2 3 4 6 7 5,8 b 1 7 3 6 4 5 8 c 7 2 6 3 5 4 1,8 d 1 2 7 3 6 4 5,8 mounting height codes code height (max) dip smd a 0.187 yes no b 0.240 yes yes c 0.290 yes yes note: codes a and b are not available for all values of t d contact technical staff for details data delay devices, inc. 3 in signal input t1-t5 tap outputs gnd ground note: standard pinout shown other pinouts available 8 7 6 5 1 2 3 4 gnd in t1 t2 gnd t5 t4 t3 delay time expressed in nanoseconds ( ns) first two digits are significant figures last digit specifies # of zeros to follow impedance expressed in nanoseconds (ns) first two digits are significant figures last digit specifies # of zeros to follow pinout code see table omit for std pinout mounting height code see table part number construction 1516(s)m - xxx - zzz p delay specifications t d t i t r attenuation (%) typical ( ns) ( ns) ( ns) z=50 w w z=100 w w z=200 w w z=300 w w z=500 w w 5 1.0 3.0 n/a 5 n/a n/a n/a 10 2.0 4.0 3 5 5 n/a n/a 15 3.0 5.0 3 5 5 n/a n/a 20 4.0 6.0 3 5 5 5 n/a 25 5.0 7.0 3 5 5 5 7 30 6.0 10.0 3 5 5 5 7 40 8.0 13.0 3 5 5 5 7 50 10.0 15.0 3 5 5 7 7 60 12.0 20.0 3 5 6 7 8 75 15.0 25.0 3 5 6 7 8 80 16.0 26.0 4 5 6 7 8 100 20.0 30.0 4 5 6 7 8 110 22.0 32.0 4 5 6 7 8 125 25.0 40.0 4 5 6 7 8 150 30.0 50.0 n/a 5 8 10 10 180 36.0 60.0 n/a 7 8 10 10 200 50.0 70.0 n/a 8 10 12 12 notes: t i represents nominal tap-to-tap delay increment tolerance on t d = 5% or 2ns, whichever is greater tolerance on t i = 5% or 1ns, whichever is greater ?n/a? indicates that delay is not available at this z 1997 data delay devices
1516 doc #97029 data delay devices, inc. 2 2/7/97 tel: 973-773- 2299 fax: 973-773-9672 http://www.datadelay.com functional diagram gnd in t5 t1 t2 t3 t4 gnd package dimensions 1516-xx (dip) see table .500 max. 1 2 3 4 5 6 7 8 .015 typ. .070 max. .018 typ. .300 .010 3 equal spaces each .100 .010 non-accumulative .280 max. .350 max. .010 .002 lead material: nickel-iron alloy 42 tin plate 1516s-xx (gull-wing) see table .520 max. 1 2 3 4 5 6 7 8 .430 typ. .020 typ. .040 typ. .100 .110 .300 .270 typ. .010 typ. .050 typ.
1516 doc #97029 data delay devices, inc. 3 2/7/97 3 mt. prospect ave. clifton, nj 07013 passive delay line test specifications test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10m w input pulse: high = 3.0v typical c load : 10pf low = 0.0v typical threshold: 50% (rising & falling) source impedance: 50 w max. rise/fall time: 3.0 ns max. ( measured at 10% and 90% levels) pulse width (t d <= 75ns): pw in = 100ns period (t d <= 75ns): per in = 1000ns pulse width (t d > 75ns): pw in = 2 x t d period (t d > 75ns): per in = 10 x t d note: the above conditions are for test only and do not in any way restrict the operation of the device. timing diagram for testing t rise t fall per in pw in t rise t fall 10% 10% 50% 50% 90% 90% 50% 50% v ih v il v oh v ol input signal output signal t rise t fall 10% 10% 90% 90% in t1 out trig in trig test setup device under test (dut) oscilloscope pulse generator 50 w r out r in r in = r out = z line t2 t3 t4 t5
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